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-- Company: 
-- Engineer:
--
-- Create Date:   13:06:52 01/22/2010
-- Design Name:   
-- Module Name:   C:/Custom32Processor/MySOC/Test_Memory.vhd
-- Project Name:  MySOC
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: MemorySample
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

-- General package
use work.GeneralProperties.ALL;
 
ENTITY Test_Memory IS
END Test_Memory;
 
ARCHITECTURE behavior OF Test_Memory IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT MemorySample
    PORT(
         CLK : IN  std_logic;
         MEM_Data : OUT  std_logic_vector((bus_size-1) downto 0);
         MEM_DataIn : IN  std_logic_vector((bus_size-1) downto 0);
         MEM_WriteAdd : IN  std_logic_vector((bus_size-1) downto 0);
         MEM_ReadAdd : IN  std_logic_vector((bus_size-1) downto 0);
         MEM_Read : IN  std_logic;
         MEM_Write : IN  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal MEM_DataIn : std_logic_vector(15 downto 0) := (others => '0');
   signal MEM_WriteAdd : std_logic_vector(15 downto 0) := (others => '0');
   signal MEM_ReadAdd : std_logic_vector(15 downto 0) := (others => '0');
   signal MEM_Read : std_logic := '0';
   signal MEM_Write : std_logic := '0';

 	--Outputs
   signal MEM_Data : std_logic_vector(15 downto 0);
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: MemorySample PORT MAP (
          CLK => CLK,
          MEM_Data => MEM_Data,
          MEM_DataIn => MEM_DataIn,
          MEM_WriteAdd => MEM_WriteAdd,
          MEM_ReadAdd => MEM_ReadAdd,
          MEM_Read => MEM_Read,
          MEM_Write => MEM_Write
        );
 
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name   
 
   CLK_process :process
   begin
		CLK <= '0';
		wait for 100 ns;
		CLK <= '1';
		wait for 100 ns;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      REPORT "Settle time ..." SEVERITY WARNING;
		wait for 200 ns;	
		
		REPORT "Read Address 0 ..." SEVERITY WARNING;
		MEM_Read <= '1';
		MEM_ReadAdd <= conv_std_logic_vector(0, bus_size);		
      wait for 200 ns;	

      REPORT "Read Address 1 ..." SEVERITY WARNING;
		MEM_Read <= '1';
		MEM_ReadAdd <= conv_std_logic_vector(1, bus_size);		
      wait for 200 ns;

      REPORT "Write Address 2 ..." SEVERITY WARNING;
		MEM_Write <= '1';
		MEM_Read <= '0';
		MEM_WriteAdd <= conv_std_logic_vector(2, bus_size);		
		MEM_DataIn   <= conv_std_logic_vector(55, bus_size);		
      wait for 200 ns;		
		
		REPORT "Read Address 3 ..." SEVERITY WARNING;
		MEM_Write <= '0';
		MEM_Read <= '1';
		MEM_ReadAdd <= conv_std_logic_vector(2, bus_size);		
      wait for 200 ns;

      -- insert stimulus here 

      wait;
   end process;

END;
